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HM658512AI series 4 m psram (512-kword 8-bit) 2 k refresh ade-203-286c(z) rev. 3.0 march 15, 1999 description the hitachi HM658512AI is a 4-mbit pseudo static ram organized 524288-word 8-bit. it realizes higher density, higher performance and low power consumption by employing 0.8 m m hi-cmos process technology. it offers low power data retention by self refresh mode. HM658512AI is suitable for handy systems which work with battery back-up systems. it is packaged in 32-pin plastic sop. features single 5 v supply: 5 v 10% high speed ? ce access time: 80 ns/100 ns/120 ns (max) ? random read/write cycle time: 130 ns/160 ns/190 ns (min) power dissipation ? active: 250 mw (typ) ? standby: 350 m w (typ) directly ttl compatible all inputs and outputs simple address configuration ? non multiplexed address refresh cycle ? 2048 refresh cycles: 32 ms easy refresh functions ? address refresh ? automatic refresh ? self refresh temperature range: C40 to +85 c
HM658512AI series 2 ordering information type no. access time package hm658512alfpi-8 hm658512alfpi-10 hm658512alfpi-12 80 ns 100 ns 120 ns 525-mil 32-pin plastic sop (fp-32d) hm658512alfpi-8v hm658512alfpi-10v hm658512alfpi-12v 80 ns 100 ns 120 ns pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we a13 a8 a9 a11 oe / rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 cc 32-pin sop (top view) pin description pin name function a0 to a18 address input i/o0 to i/o7 data input/output ce chip enable oe / rfsh output enable/refresh we write enable v cc power supply v ss ground
HM658512AI series 3 block diagram refresh control timing pulse generator read write control address latch control column decoder column i/o memory matrix row decoder address latch control input data control ce we i/o 7 i/o 0 a0 a10 a11 a18 oe / rfsh (2048 256) 8 pin functions ce (input) : ce is a basic clock. ram is active when ce is low, and is on standby when ce is high. a0 to a18 (input): a0 to a10 are row addresses and a11 to a18 are column addresses. the entire addresses a0 to a18 are fetched into ram by the falling edge of ce . oe / rfsh (input) : this pin has two functions. basically it works as oe when ce is low, and as rfsh when ce is high (in standby mode). after a read or write cycle finishes, refresh does not start if ce goes high while oe / rfsh is held low. in order to start a refresh in standby mode, oe / rfsh must go high to reset the refresh circuits of the ram. after the refresh circuits are reset, the refresh starts when oe / rfsh goes low. i/o0 to i/o7 (inputs and outputs) : these pins are data i/o pins. we (input): ram is in write mode when we is low, and is in read mode when we is high. i/o data is fetched into ram by the rising edge of we or ce (earlier timing) and the data is written into memory cells.
HM658512AI series 4 notes refresh there are three refresh modes : address refresh, automatic refresh and self refresh. (1) address refresh: data is refreshed by accessing all 2048 row addresses every 32 ms. a read is one method of accessing those addresses. each row address (2048 addresses of a0 to a10)must be read at least once every 32 ms. in address refresh mode, oe / rfsh can remain high. in this case, the i/o pins remain at high impedance, but the refresh is done within ram. (2) automatic refresh: instead of address refresh, automatic refresh can be used. ram goes to automatic refresh mode if oe / rfsh falls while ce is high and it remains low for at least t fap . one automatic refresh cycle is executed by one low pulse of oe / rfsh . it is not necessary to input the refresh address from outside since it is generated internally by an on-chip address counter. 2048 automatic refresh cycles must be done every 32 ms. (3) self refresh: self refresh mode is suitable for data retention by battery. in standby mode, a self refresh starts automatically when oe / rfsh stays low for more than 8 m s. refresh addresses are automatically specified by the on-chip address counter, and the refresh period is determined by the on-chip timer. automatic refresh and self refresh are distinguished from each other by the width of the oe / rfsh low pulse in standby mode. if the oe / rfsh low pulse is wider than 8 m s, ram becomes into self refresh mode; if the oe / rfsh low pulse is less than 8 m s, it is recognized as an automatic refresh instruction. at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and oe / rfsh must be kept high. if auto refresh follows self refresh, low transition of oe / rfsh at the beginning of automatic refresh must not occur during t rfs period. others since pseudo static ram consists of dynamic circuits like dram, its clock pins are more noise-sensitive than conventional srams. (1) if a short ce pulse of a width less than t ce min is applied to ram, an incomplete read occurs and stored data may be destroyed. make sure that ce low pulses of less than t ce min are inhibited. note that a 10 ns ce low pulse may sometimes occur owing to the gate delay on the board if the ce signal is generated by the decoding of higher address signals on the board. avoid these short pulses. (2) oe / rfsh works as refresh control in standby mode. a short oe / rfsh low pulse may cause an incomplete refresh that will destroy data. make sure that oe / rfsh low pulse of less than t fap min are also inhibited. (3) t ohc and t ocd are the timing specs which distinguish the oe function of oe / rfsh from the rfsh function. the t ohc and t ocd specs must be strictly maintained. (4) start the HM658512AI operating by executing at least eight initial cycles (dummy cycles) at least 100 m s after the power voltage reaches 4.5 v to 5.5 v after power-on.
HM658512AI series 5 operation table ce oe / rfsh we i/o operation l l h dout read l l high-z write l h h high-z hl high-z refresh hh high-z standby note: h; v ih , l; v il , ; v ih or v il absolute maximum ratings parameter symbol value unit note terminal voltage with respect to v ss v t C1.0 to +7.0 v 1 power dissipation p t 1.0 w storage temperature range tstg C55 to +125 c storage temperature range under bias tbias C40 to +85 c note: 1. with respect to v ss dc operating conditions parameter symbol min typ max unit notes supply voltage v cc 4.5 5.0 5.5 v v ss 000 v input high voltage v ih 2.8 6.0 v input low voltage v il C1.0 0.8 v 1 ambient temperature range ta C40 +85 c note: 1. v il min = C3.0 v for pulse width 30 ns
HM658512AI series 6 dc characteristics parameter symbol min typ max unit test conditions notes operating power supply current i cc1 75 ma i i/o = 0 ma, t cyc = min standby power supply current i sb1 12ma ce = v ih , vin 3 0 v oe / rfsh = v ih i sb2 20 200 m a ce 3 v cc C 0.2 v, vin 3 0 v, oe / rfsh 3 v cc C 0.2 v operating power supply current in self refresh mode i cc2 12ma ce = v ih , vin 3 0 v, oe / rfsh = v il i cc3 70 200 m a ce 3 v cc C 0.2 v, vin 3 0 v, oe / rfsh 0.2 v input leakage current i li C10 10 m av cc = 5.5 v, vin = v ss to v cc output leakage current i lo C10 10 m a oe / rfsh = v ih v i/o = v ss to v cc output voltage v ol 0.4 v i ol = 2.1 ma v oh 2.4 v i oh = C1 ma capacitance (ta = 25 c, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance c in 8 pf v in = 0 v input /output capacitance c i/o 10 pfv i/o = 0 v note : this parameter is sampled and not 100% tested. ac characteristics (ta = C40 to +85 c, v cc = 5 v 10%, unless otherwise noted.) test conditions input pulse levels: 0.4 v, 2.8 v input rise and fall time: 5 ns timing measurement level: 0.8 v, 2.2 v reference levels: v oh = 2.0 v, v ol = 0.8 v output load: 1 ttl gate and c l (100 pf) (including scope and jig)
HM658512AI series 7 HM658512AI -8 -10 -12 parameter symbol min max min max min max unit notes random read or write cycle time t rc 130 160 190 ns chip enable access time t cea 80 100 120 ns read-modify- write cycle time t rwc 180 220 260 ns output enable access time t oea 30 40 50 ns chip disable to output in high-z t chz 0 25 0 25 0 30 ns 1, 2 chip enable to output in low-z t clz 20 20 20 ns 2 output disable to output in high-z t ohz 25 25 25 ns 1, 2 output enable to output in low-z t olz 0 0 0 ns2 chip enable pulse width t ce 80 n 10 m 100 n 10 m 120 n 10 m s chip enable precharge time t p 40 50 60 ns address setup time t as 0 0 0 ns address hold time t ah 20 25 30 ns read command setup time t rcs 0 0 0 ns read command hold time t rch 0 0 0 ns write command pulse width t wp 25 30 35 ns chip enable to end of write t cw 80 100 120 ns chip enable to output enable delay time t ocd 0 0 0 ns output enable hold time t ohc 0 0 0 ns data in to end of write t dw 20 25 30 ns data in hold time for write t dh 0 0 0 ns output active from end of write t ow 5 5 5 ns2 write to output in high-z t whz 20 25 30 ns 1, 2 transition time (rise and fall) t t 350350350ns6
HM658512AI series 8 HM658512AI -8 -10 -12 parameter symbol min max min max min max unit notes refresh command delay time t rfd 40 50 60 ns refresh precharge time t fp 40 40 40 ns refresh command pulse width for automatic refresh t fap 80 n 8 m 80 n 8 m 80 n 8 m s automatic refresh cycle time t fc 130 160 190 ns refresh command pulse width for self refresh t fas 8 8 8 m s refresh reset time from self refresh t rfs 600 600 600 ns 9 refresh period t ref 32 32 32 ms 2048 cycle notes: 1. t chz , t ohz , t whz are defined as the time at which the output achieves the open circuit condition. 2. t chz , t clz , t ohz , t olz , t whz and t ow are sampled under the condition of t t = 5 ns and not 100% tested. 3. a write occurs during the overlap of low ce and low we . write end is defined at the earlier of we going high or ce going high. 4. if the ce low transition occurs simultaneously with or from the we low transition, the output buffers remain in high impedance state. 5. in write cycle, oe or we must disable output buffers prior to applying data to the device and at the end of write cycle data inputs must be floated prior to oe or we turning on output buffers. during this period, i/o pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. transition time t t is measured between v ih (min) and v il (max). v ih (min) and v il (max) are reference levels for measuring timing of input signals. 7. after power-up, pause for more than 100 m s and execute at least 8 initialization cycles. 8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed within 15 m s after self refresh, in order to meet the refresh specification of 32 ms and 2048 cycles. 9. at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and oe / rfsh must be kept high. if automatic refresh follows self refresh, low transition of oe / rfsh at the beginning of automatic refresh must not occur during t rfs period.
HM658512AI series 9 timing waveform read cycle t ce address a0 to a18 we oe / rfsh t t tt valid t t t t dout t valid data out t t t rc ce as ah p rch chz ohz oea cea ohc rcs olz
HM658512AI series 10 write cycle (1) ( oe = v ih ) ce address a0 to a18 we oe / rfsh din t t t tt valid dout valid data in t t tt t t t t t t rc ce as ah cw clz ohz whz wp ocd p dw dh olz ow
HM658512AI series 11 write cycle (2) ( oe = v il ) ce address a0 to a18 we din t t t tt valid dout valid data in t t t t t t t t rc ce p dh cw wp dh dw whz clz ohc ah as oe / rfsh
HM658512AI series 12 read-modify-write cycle ce address a0 to a18 we din t t t tt valid dout valid data in t t t t t t t t t valid data out t t t t t t rwc ce cw p rch ocd wp dh dw chz ow as ah rcs cea ohc oea olz clz ohz oe / rfsh automatic refresh cycle ce oe / rfsh tt t tt tt rfd fc fp fap fp fap fc
HM658512AI series 13 self refresh cycle ce t t t t rfd fp fas rfs oe / rfsh low v cc data retention characteristics (ta = C40 to +85 c) this characteristics is guaranteed only for v-version. parameter symbol min typ max unit test conditions v cc for data retention v dr 3.6 5.5 v self refresh current i ccdr 200 m av cc = 3.6 v, ce 3 v cc C 0.2 v oe / rfsh 0.2 vin 3 0 v 200 m av cc = 5.5 v, ce 3 v cc C 0.2 v oe / rfsh 0.2 vin 3 0 v refresh setup time t fs 0 ns operation recovery time t fr 5 ms
HM658512AI series 14 low v cc data retention timing waveform data retention mode vdr fas fs fr rfs t fp 4.5 v 2.8 v 0.8 v 2.8 v 0.8 v ce oe / rfsh ce 3 v cc ?0.2v oe / rfsh 0.2v v cc rfd t tt t t notes: 1. rise time and fall time of power supply voltage must be smaller than 0.05 v/ms. 2. keep ce 3 v cc ?0.2 v during data retention mode. 3. regarding t rfd , t fp , t fas and t rfs , refer to ac characteristics. 4. input voltage should be lower than v cc +1.5 v in data retention mode.
HM658512AI series 15 package dimensions hm658512alfpi series (fp-32d) hitachi code jedec eiaj weight (reference value) fp-32d conforms ? 1.3 g unit: mm *dimension including the plating thickness base material dimension 0.15 m *0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max *0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04
HM658512AI series 16 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products.
HM658512AI series 17 hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: revision record rev. date contents of modification drawn by approved by 0.0 jul. 15, 1994 initial issue h. uchida m. watanabe 1 nov. 3, 1994 deletion of preliminary k. imato k. yoshizaki 2.0 apr. 20, 1995 addition of hm658512 afpi-8 series ac characteristics t rc min: 160/190 ns to 130/160/190 ns t cea max: 100/120 ns to 80/100/120 ns t rwc min: 220/260 ns to 180/220/260 ns t oea max: 40/50 ns to 30/40/50 ns t chz min: 0/0 ns to 0/0/0 ns t chz max: 25/30 ns to 25/25/30 ns t clz min: 20/20 ns to 20/20/20 ns t ohz max: 25/25 ns to 25/25/25 ns t olz min: 0/0 ns to 0/0/0 ns t ce min: 100/120 ns to 80/100/120 ns t ce max: 10000/10000 ns to 10000/10000/10000 ns t p min: 50/60 ns to 40/50/60 t as min: 0/0 ns to 0/0/0 ns t ah min: 25/30 ns to 25/25/30 ns t rcs min: 0/0 ns to 0/0/0 ns t rch min: 0/0 ns to 0/0/0 ns t wp min: 30/35 ns to 25/30/35 ns t cw min: 100/120 ns to 80/100/120 ns t ocd min: 0/0 ns to 0/0/0 ns t ohc min: 0/0 ns to 0/0/0 ns t dw min: 25/30 ns to 25/25/30 ns t dh min: 0/0 ns to 0/0/0 ns t ow min: 5/5 ns to 5/5/5 ns k. imato k. yoshizaki
HM658512AI series 18 t whz max: 25/30 ns to 25/25/30 ns t t min: 3/3 ns to 3/3/3 ns t t max: 50/50 ns to 50/50/50 ns t rfd min: 50/60 ns to 40/50/60 t fp min: 40/40 ns to 40/40/40 ns t fap min: 80/80 ns to 80/80/80 ns t fap max: 8000/8000 ns to 8000/8000/8000 ns t fc min: 160/190 ns to 130/160/190 ns t fas min: 8/8 m s to 8/8/8 m s t rfs min: 600/600 ns to 600/600/600 ns t ref max: 32/32 ms to 32/32/32 ms revision record (cont.) rev. date contents of modification drawn by approved by 3.0 mar. 15, 1999 change data sheet title hm658128afpi series to HM658512AI series change format description deletion of description about temperature range features addition of temperature range: C40 to +85 c deletion of hm658512adfpi series dc characteristics deletion of note 1 ac characteristics deletion of note 10 correct error of low v cc data retention timing waveform: 2.4 v to 2.8 v

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